1. Field of the Invention
The present invention relates to an electronic circuit apparatus for transmitting signals through a bus. Further, the present invention also relates to a semiconductor device for generating a predetermined stable voltage.
2. Description of the Related Art
An electronic circuit apparatus is arranged on a printed board (mother board). The mother board, for example, comprises an MPU (microprocessor unit), a data transmission bus (data bus lines), a memory unit (memory modules), various extended boards, and the like.
By the way, clock frequencies of MPUs today are in excess of 100 MHz. Further, DRAMs (dynamic random access memories), used as a main memory, are built as the data server to cache memories in modern microprocessor systems. They operate mostly in burst-mode rather than in random access mode, in order to re-write the data in cache memories. High bandwidth memories such as SDRAMs (synchronous DRAMs) are thus useful for high-speed implementation in the burst-mode, along with high-speed I/O circuits for the bus interface.
Therefore, high performance I/O circuits for fast memory such as SDRAMs are now required. The problems of the prior art relating to a first aspect of the present invention (electronic circuit apparatus for transmitting signals through a bus) will be explained hereafter in detail with reference to the accompanying drawings.
On the other hand, recently, semiconductor devices must be compact and operate at a high speed and low power consumption. To realize this, it is necessary to provide the semiconductor devices with a high-speed clock signal and a low source voltage.
Namely, it is necessary to provide a semiconductor circuit capable of providing a stable source voltage as a cell plate voltage for a semiconductor memory such as a DRAM, or as a reference voltage for a small-amplitude I/O device. The problems of the prior art relating to a second aspect of the present invention (semiconductor device for generating a predetermined stable voltage) will be also explained hereafter in detail with reference to the accompanying drawings.
An object of the present invention (first aspect of the present invention) is to provide an electronic circuit apparatus for transmitting signals through a bus, capable of suppressing a ringing in a stub, preventing a delay in transmitting signals, increasing a transmission frequency, and improving a transmission speed.
Further, another object of the present invention (second aspect of the present invention) to provide a semiconductor circuit realizing a small output impedance at low power consumption.
According to a first aspect of the present invention, there is provided an electronic circuit apparatus having a bus, a plurality of stubs branched from the bus, and a plurality of semiconductor devices having signal input/output terminals connected to the corresponding stubs, wherein the electronic circuit apparatus comprises at least one impedance circuits arranged between the bus and at least one of the stubs, and each of the impedance circuit has a high-pass filter characteristic.
At least one end of the bus may be terminated by terminating resistor or both ends of the bus may be terminated by terminating resistors. A resistance value of the terminating resistor may be determined in a range of 25 to 75 ohms. In the electronic circuit apparatus, fxc3x97d may be equal to or smaller than 5xc3x97106; where f is a basic component frequency (Hz) of a signal transmitted through the bus, and d is a length (meters) of the stub.
The bus may be connected to a terminal voltage supplying line through the terminating resistor. The terminal voltage supplying line may be connected to a high potential power supply line through a first stabilizing capacitor and a low power supply line through a second stabilizing capacitor. The first and second stabilizing capacitors may be provided at both ends of the terminal voltage supplying line, and each end of the bus may be connected to an intermediate connection portion between the first and second stabilizing capacitors through the corresponding terminating resistor.
Further, according to a first aspect of the present invention, there is provided a connector for connecting a plurality of semiconductor devices having signal input/output terminals to corresponding stubs, the stubs being branched from a bus, wherein the connector comprises at least one impedance circuit arranged between the semiconductor devices and the stubs.
In addition, according to a first aspect of the present invention, there is also provide a memory module connected to a bus through a plurality of stubs branched from the bus, the memory module comprising a plurality of semiconductor memories having signal input/output terminals connected to the corresponding stubs, wherein the memory module comprises at least one impedance circuits arranged between the stubs and the semiconductor memories.
The impedance circuit has a high-pass filter characteristic, and is used to prevent ringing. The impedance circuit may be formed as an integrated element. The impedance circuit may comprises a resistor and a capacitor connected in parallel with the first resistor.
The impedance circuit may comprise a first resistor, a second resistor, and a capacitor, wherein the second resistor and the capacitor may be connected in series therewith and are connected in parallel with the first resistor.
A resistance value of the resistor may be determined to prevent ringing and to match an impedance of the stub with an impedance of the bus. A resistance value of the resistor may be determined in a range of 25 to 100 ohms, and a capacitance value of the capacitor may be determined in a range of 10 to 50 picofarads.
The impedance circuit may comprises a first resistor, a second resistor, and a capacitor, wherein the second resistor and the capacitor may be connected in parallel therewith and may be connected in series with the first resistor.
The first resistor and the second resistor may constitute one resistor, and a resistance value of the resistor may be determined to prevent ringing and to match an impedance of the stub with an impedance of the bus. A resistance value of the resistor may be determined in a range of 25 to 100 ohms, and a capacitance value of the capacitor may be determined in a range of 10 to 50 picofarads. A resistance value of the first resistor may be determined in a range of 5 to 20 ohms.
The impedance circuit may comprise a first resistor, a second resistor, and a capacitor, wherein the first resistor may be connected in series between the bus and the stub, one end of the second resistor may be connected to the bus and another end of the second resistor may be electrically open, and the capacitor may be arranged between the first resistor and the second resistor for constituting a distributed constant circuit.
A resistance value of the first resistor may be determined to prevent ringing and to match an impedance of the stub with an impedance of the bus. A resistance value of the first resistor may be determined in a range of 25 to 100 ohms.
The bus may be a data bus. An impedance circuit identical to that defined by the impedance circuit may be connected to an output of a driver that transmits a signal received through another bus to the semiconductor devices. The another bus may be an address bus.
The electronic circuit apparatus may be a mother board. The electronic circuit apparatus may be a mother memory board.
According to a second aspect of the present invention, there is provided a semiconductor circuit comprising a first power source unit, a second power source unit, a plurality of first-conductivity transistors, a plurality of second-conductivity transistors, the transistors being connected in series between the first and second power source units, and an output node between the first-conductivity transistor and the second-conductivity transistor, for providing an output.
A number of the series-connected second-conductivity transistors may be the same as a number of the series-connected first-conductivity transistors, and an arrangement of the transistors between the first power source unit and the output node may be the same as an arrangement of the transistors between the output node and the second power source unit. The first power source unit may be of high potential, the second power source unit may be of low potential, the first-conductivity transistors may be p-channel MOS transistors, and the second-conductivity transistors may be n-channel MOS transistors. A total number of the first-conductivity transistors and the second-conductivity transistors may be 4 by n; where n is a natural number.
A voltage of the output is an intermediate voltage between a voltage of the first power source unit and a voltage of the second power source unit. The first-conductivity transistors and the second-conductivity transistors may form diodes, respectively. The output may be connected to a control electrode of the first-conductivity transistor connected to the first power source unit and to a control electrode of the second-conductivity transistor connected to the second power source unit.
The output may serve as the substrate or well potential of the transistors other than the transistors that are connected to the first and second power source units, respectively. The difference between the threshold voltages of the first- and second-conductivity transistors may be equal to or less than 10% of a power source voltage.
The semiconductor circuit may further comprise a second-conductivity transistor and a first-conductivity transistor, these transistors being connected in series between the first power source unit and the second power source unit and forming a second output section that provides a second output, which is different from the first output. The second output may be provided from a node between the second-conductivity transistor and the first-conductivity transistor in the second output section, control electrodes of the transistors of the second output section may be connected to control electrodes of the transistors of the first output section, respectively.
The first output may serve as a substrate or well potential of the transistors of the second output section to provide the second output. An output from a control circuit may be applied to a control electrode of the first-conductivity transistor connected to the first power source unit and to a control electrode of the second-conductivity transistor connected to the second power source unit in the first output section, to accurately adjust the outputs.
The semiconductor circuit may further comprise a resistor arranged between the control circuit and the control electrodes of the transistors of the first output section. The control circuit may detect a difference between the first or second output and a reference voltage.
The second output may serve as a substrate or well potential of the transistors of the second output section to provide the second output. An output from a control circuit may be applied to a control electrode of the first-conductivity transistor connected to the first power source unit and to a control electrode of the second-conductivity transistor connected to the second power source unit in the first output section, to accurately adjust the outputs.
The semiconductor circuit may further comprise a resistor arranged between the control circuit and the control electrodes of the transistors of the first output section. The control circuit may detect a difference between the first or second output and a reference voltage.
The second output section may have a first-conductivity transistor arranged between the first power source units and the second-conductivity transistor, and a second-conductivity transistor arranged between the second power source unit and the first-conductivity transistor.
The second output may be connected to the control electrode of the first-conductivity transistor connected to the first power source unit and to the control electrode of the second-conductivity transistor connected to the second power source unit in the first output section. The first output may be connected to the control electrode of the first-conductivity transistor connected to the first power source unit and to the control electrode of the second-conductivity transistor connected to the second power source unit in the second output section.